Design of Cost-Efficient Interconnect Processing Units

Streamlined Design Solutions Specifically for NoC how the SoC and NoC technology workswhy developers designed it the way they didthe system-level design methodology and tools used to configure the Spidergon STNoC architecturedifferences in cost structure between NoCs and system-level networksFrom professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors – all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.